1. Field of the Invention
This invention relates to semiconductor memories and more particularly to devices with high capacitive coupling ratios.
2. Description of Related Art
Referring to FIG. 8, a conventional prior art split gate device is shown which includes a P- substrate 40 with N+ S/D regions 47, 47' on either side of a polysilicon 1 floating gate 48 and a polysilicon 2 control gate 56. The edge of the floating gate 48 is adjacent to one region 47'of the S/D regions but spaced away from the other region 47. The control gate 56 however, which overlies the floating gate 48 reaches the edge of the other region 47 of the S/D regions and its edge which is distal from the floating gate 48. Gate oxide is located between the control gate 56 and substrate 40. A thicker oxide layer 52 is formed between floating gate 48 and substrate 40. Samachisa et al "A 128k Flash EEPROM Using Double-Polysilicon Technology" IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, pp 676-683, (October 1987) shows a conventional prior art split gate structure of the kind illustrated by FIG. 8.
U.S. Pat. No. 5,045,488 of Yeh for "Method of Manufacturing a Single Transistor Non-Volatile, Electrically Alterable Semiconductor Memory Device" and U.S. Pat. No. 4,988,635 of Ajika et al for "Method of Manufacturing Non-Volatile Semiconductor Memory Device" show processes for manufacturing EPROM devices.